The present invention relates to a technology of minimizing a mismatch between a termination circuit and a calibration circuit of an on-die termination (ODT) device used for impedance matching in a semiconductor memory device.
Semiconductor devices are implemented into integrated circuit (IC) chips such as central processing units (CPUs), memories, and gate arrays, and are incorporated into a variety of electrical products such as personal computers, servers and workstations. Most semiconductor devices include a receiving circuit configured to receive signals from the outside via input pads and an output circuit configured to provide internal signals to the outside via output pads.
A tendency toward high-speed operation of such electronic products brings about a small swing width for an interface signal between the semiconductor devices, in order to reduce a delay time taken in signal transfer. However, such a trend to gradually reduce the swing width of the signal influences external noise, and further, signal reflection caused by impedance mismatch in an interface terminal becomes critical. Such impedance mismatch is generally caused by external noise, variation of power supply voltage, change in operating temperature, change in manufacturing process, etc. The impedance mismatch may lead to difficulty in high-speed transmission of data and distortion in output data. If a distorted output signal is transmitted, a set-up/hold time failure or an input level decision error, etc., may often occur at a receiving side.
In particular, in order to resolve the above problems, a memory device requiring high-speed performance employs an impedance matching circuit, which is called an ODT circuit, near an input pad inside an IC chip. In a typical ODT scheme, source termination is performed at the transmitting end by an output circuit, and parallel termination is performed by a termination circuit connected in parallel with respect to a receiving circuit coupled to the input pad.
ZQ calibration refers to a procedure of generating pull-up and pull-down calibration codes which vary with PVT (process, voltage and temperature) conditions. The resistance of the ODT device, e.g., termination resistance at a DQ pad in a memory device, is calibrated using the pull-up and pull-down codes achieved from the ZQ calibration. Here, the term of ZQ calibration is derived from the fact that the calibration is performed using a calibration node (ZQ).
Hereinafter, how the ZQ calibration is performed in an ODT device will be described.
FIG. 1 is a block diagram of a calibration circuit configured to perform ZQ calibration in a conventional ODT device.
Referring to FIG. 1, the conventional ODT device includes a pull-up calibration resistor unit 110, a dummy calibration resistor unit 120, a pull-down calibration resistor unit 130, a reference voltage generator 102, comparators 103 and 104, and counters 105 and 106. The pull-up calibration resistor unit 110 includes a plurality of pull-up resistors, which are turned on/off in response to each of pull-up calibration codes PCODE<0:N>. The dummy calibration resistor unit 120 has the same configuration as the pull-up calibration resistor unit 110. The pull-down calibration resistor unit 130 includes a plurality of pull-down, resistors which are turned on/off in response to each of pull-down calibration codes NCODE<0:N>.
The pull-up calibration resistor unit 110 generates the pull-up calibration codes PCODE<0:N> primarily while being calibrated with an external resistor 101 connected to a calibration node ZQ. The dummy calibration resistor unit 120 and the pull-down calibration resistor unit 130 generate the pull-down calibration codes NCODE<0:N> secondarily using the pull-up calibration codes PCODE<0:N> that have been generated by the pull-up calibration resistor unit 110.
The comparator 103 compares a voltage at the calibration node ZQ with a reference voltage VREF (generally set to VDDQ/2) generated from the reference voltage generator 102, thereby generating up/down signals (UP/DOWN). Herein, the voltage at the calibration node ZQ is generated by coupling the pull-up calibration resistor unit 110 to the external resistor 101 (generally, 240Ω) connected to a ZQ pin that is disposed outside a chip of the calibration node ZQ.
The counter 105 receives the up/down signals (UP/DOWN) to generate the pull-up calibration codes PCODE<0:N> as binary code, which turns on/off the pull-up resistors connected in parallel, thereby calibrating total resistance of the pull-up calibration resistor unit 110. The calibrated resistance of the pull-up calibration resistor unit 110 affects the voltage of the calibration node ZQ again, and the above-described calibration procedure is then repeated. That is, the pull-up calibration resistor unit 110 is calibrated such that the total resistance of the pull-up calibration resistor unit 110 is equal to the resistance of the external resistor 101, which is called a pull-up calibration.
The binary code, i.e., the pull-up calibration codes PCODE<0:N> generated during the pull-up calibration, is inputted to the dummy calibration resistor unit 120, thus determining total resistance of the dummy calibration unit 120. In the result, the resistance of the dummy calibration resistor unit 120 is equal to that of the pull-up calibration unit 110. Thereafter, a pull-down calibration is performed in a manner similar to the pull-up calibration. Specifically, the pull-down calibration unit 130 is calibrated such that a voltage at a node A is equal to the reference voltage VREF using the comparator 104 and the counter 106, that is, the total resistance of the pull-down calibration resistor unit 130 is equal to the total resistance of the dummy calibration resistor unit 120, which is called a pull-down calibration.
The binary codes PCODE<0:N> and NCODE<0:N> achieved from the ZQ calibration, i.e., pull-up and pull-down calibrations, are inputted to pull-up and pull-down resistors (termination resistors) at input/output pads, which are similarly configured in the pull-up and pull-down calibration resistor units 110 and 130 of the calibration circuit shown in FIG. 1, thus determining the resistance of the ODT device. In a memory device, resistances of pull-up and pull-down resistors at a DQ pad are determined.
FIG. 2 is a block diagram illustrating how termination resistance of an output driver (termination circuit) of a semiconductor memory device is determined using the calibration codes PCODE<0:N> and NCODE<0:N> generated from the calibration circuit of FIG. 1.
The output driver configured to output data in the semiconductor memory device includes pre-drivers 210 and 220 provided in up/down circuits, and pull-up and pull-down termination resistor units 230 and 240 for outputting data.
The pre-drivers 210 and 220 provided in the up/down circuits control the pull-up termination resistor unit 230 and the pull-down resistor unit 240, respectively. When high-level data is outputted, the pull-up termination resistor unit 230 is turned on so that a data pin DQ goes ‘HIGH’. On the contrary, when low-level data is outputted, the pull-down termination resistor unit 240 is turned on so that the data pin DQ goes ‘LOW’. That is, the data pin DQ is pull-up or pull-down terminated to thereby output high- or low-level data.
The number of resistors in the pull-up termination resistor unit 230 to be turned on is determined by the pull-up calibration codes PCODE<0:N>, and the number of resistors in the pull-down termination resistor unit 240 to be turned on is determined by the pull-down calibration codes NCODE<0:N>. Specifically, which one is turned on as between the pull-up and pull-down termination resistor units 230 and 240 is mainly determined according to a logic level of output data, but how many resistors are turned on among the resistors provided in the termination resistor units 230 or 240 is determined by the pull-up calibration codes PCODE<0:N> or the pull-down calibration codes NCODE<0:N>.
For reference, target resistances of the pull-up and pull-down termination resistor units 230 and 240 are not necessarily equal to resistances (240Ω) of the calibration resistor units (see calibration resistor units 110, 120 and 130 of FIG. 1), but may be one-half (120Ω) or one-quarter (60Ω) of 240Ω, etc. Since the termination resistance may be changed according to an application system, the termination resistor units 230 and 240 for 240 Ω, 120Ω and 60Ω are all provided and they may be selectively used if necessary. In FIG. 2, reference symbols DQP_CTRL and DQN_CTRL denote various exemplary control signals inputted to the pre-drivers 210 and 220.
The calibration operation of the ODT device is proposed assuming that the calibration units 110 and 130 of the calibration circuit of FIG. 1 have the same configurations as the termination resistor units 230 and 240 of the termination circuit of FIG. 2, and thus they are equally affected by PVT variations. However, the configuration at a side of the ZQ pad of the calibration circuit of FIG. 1 is not completely identical to the configuration at a side of the DQ pad of the termination circuit of FIG. 2. For example, while the pull-up calibration resistor unit 110 is connected to the calibration node ZQ and the pull-down calibration resistor unit 130 is connected to the node A in the calibration circuit of FIG. 1, both of the pull-up and pull-down termination resistor units 230 and 240 of the termination circuit of FIG. 2 are connected to the DQ pad. Further, there is a difference in target resistance between the calibration circuit of FIG. 1 and the termination circuit of FIG. 2. Therefore, a mismatch inevitably exists between the calibration circuit of FIG. 1 and the termination circuit of FIG. 2.
Consequently, even after the calibration operation is performed, the termination resistance of the termination circuit still may be lower or greater than the target resistance.